Programmable logic devices such as field programmable gate arrays (FPGAs) implement their logic through look-up tables. Each look-up table (LUT) includes a plurality of memory cells such as SRAM cells that store the corresponding truth table. For example, a 16-bit LUT would include 16 memory cells storing a 16-bit truth table. Based upon the input signal to the LUT, one of the values in the truth table is provided as the resulting look-up table logic output signal. To perform the selection of the appropriate value from the truth table responsive to the input signals, a look-up table will typically include a number of pass gates. Each pass gate may be constructed using an NMOS transistor. The resulting LUT may then be designated as an NMOS-based LUT. Alternatively, the pass gates may be implemented using transmission gates. As used herein, LUTs that use transmission gates as the pass gates are denoted as “CMOS-based” LUTs since a transmission gate includes both an NMOS transistor and a PMOS transistor. It is the case, however, that NMOS-based LUTs also include PMOS devices and so they may also be constructed using CMOS process technology. But since the pass gates are not complementary (including both an NMOS as well as a PMOS device) in a NMOS-based LUT, only LUTs having their pass gates implemented as transmission gates are denoted herein as CMOS-based LUTs.
An example 16-bit NMOS-based LUT 100 is shown in FIG. 1A. Signals A, B, C, and D are the input signals to LUT 100. Input signals A and B are decoded by a decoder 105 to produce a four decoded signals S(3:0). The sixteen bits for LUT 100 are split into four 4-bit LUTs, ranging from a LUT0, a LUT1, a LUT2, to a LUT3. The decoded signals S(3:0) are received by the 4-bit LUTs. An example 4-bit LUT 135 is shown in FIG. 1B. The 4 bits are stored in memory cells ranging from a bit 0 cell, a bit 1 cell, a bit 2 cell, to a bit 3 cell. The complement bit value QN for each memory cell is inverted through a corresponding inverter before passing through a corresponding pass transistor. From the decoded signals S(3:0), S(0) drives the gate of an NMOS pass transistor M4 for bit cell 0. Similarly, S(1) drives the gate of an NMOS pass transistor M5 for bit cell 1, S(2) drives the gate of an NMOS pass transistor M6 for bit cell 2, and S(3) drives the gate of an NMOS pass transistor M7 for bit cell 3. Referring again to decoder 105 of FIG. 1A, the two signals A and B may be decoded such that only one of the decoded signals S(3:0) is asserted such that only the corresponding pass transistor M4 through M7 (FIG. 1B) will allow the corresponding bit to pass.
The remaining input signals C and D and their inverted versions CN and DN control which 4-bit LUT output signal can produce the output signal for LUT 100. Inverted control signal CN drives the gate of an NMOS pass transistor M0 to control whether the output of LUT 0 passes to an inverter 110 whereas control signal C drives the gate of an NMOS pass transistor M1 to control whether the output of LUT 1 passes to inverter 110. The same control for whether LUT 2 passes its output signal to an inverter 115 and for whether LUT 3 passes its output signal to inverter 115 exists with regard to NMOS pass transistors M2 and M3. Consider the case as the supply voltage VCC is lowered for more advanced process nodes. Should pass transistors M0 through M3 have to pass a binary one output signal (which should be at the power supply voltage VCC), the resulting passed output signal will be lowered in voltage by the threshold voltage Vt for these pass transistors. For example, if the power supply voltage VCC is 0.9 volts and Vt is 0.45 volts, the resulting passed binary high signal to either inverter 110 and 115 would be only 0.45 volts. For such a relatively low voltage to be detected as a logic high signal, the threshold voltage of the NMOS transistor (not illustrated) in inverters 110 and 115 must be relatively low whereas the PMOS transistor (not illustrated) in these same inverters must have a relatively high threshold voltage. To ensure that the PMOS transistor in each inverter 110 and 115 is fully off with such a weak binary one signal coming from pass transistors M0 through M3, the output of the inverters feeds back through to their inputs through PMOS transistors P0 and P1, respectively. But the low Vt for the NMOS transistors in inverters 110 and 115 then results in these NMOS transistors not fully turning off when the inverters receive logic low (ground) input signals. The result is relatively high static power consumption for an NMOS-based LUT such as LUT 100.
To complete the operation of LUT 100, the output of inverter 110 is gated by a transmission gate 120 having a PMOS side controlled by input signal D and an NMOS side controlled by inverted input signal D. Similarly, the output of inverter 115 is gated by a transmission gate 125 having its PMOS side controlled by inverted input signal DN and its NMOS side controlled by input signal D. Transmission gates 120 and 125 drive an inverter 130 that produces the LUT output signal accordingly. The result is that the four input signals A, B, C, and D select for one of the sixteen truth table bits as would be expected for a sixteen-bit LUT operation.
To lower the static power consumption, pass transistors M0 through M3 in LUT 100 may be replaced with transmission gates as is conventional for a CMOS-based LUT. Inverters 110 and 115 may then use high-VT NMOS transistors, which reduces the static power consumption. But the PMOS transistors in the resulting transmission gates introduce additional capacitance, which lowers operating speeds. In addition, the need for the additional PMOS transistors to construct the resulting transmission gates reduces density as compared to NMOS-based LUTs.
Accordingly, there is a need in the art for an NMOS-based LUT with decreased static power consumption.
Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.